void TD_Init( void )
{ // Called once at startup
CPUCS= 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
SYNCDELAY;
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
PINFLAGSAB= 0x08; // FLAGA- EP2EF（EP2空标志）//EP2 OUT
SYNCDELAY;
PINFLAGSCD = 0x0E; // FLAGC - EP6FF（EP6满标志）//EP6 IN
SYNCDELAY;
//PORTACFG|= 0x80; //PA7复用为FLAGD
//SYNCDELAY;
IFCONFIG= 0x63; //Internal clock, 48 MHz, Slave FIFO interface
//设置为0x63时为externalclock,5MHz-48MHz
SYNCDELAY;
//IFCONFIG 寄存器的位定义信息
//IFCLKSRC=1 , FIFOs executes on internalclk source
//xMHz=1 , 48MHz operation
//IFCLKOE=1 ,Drive IFCLK pin signal at48MHz
//IFCLKPOL=0 , Don't invert IFCLK pinsignal from internal clk
//ASYNC=0 , master samples synchronous
//GSTATE=0 , Don't drive GPIF statesout on PORTE[2:0], debug WF
//IFCFG[1:0]=11, FX2 in slave FIFO mode
//Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced byGPIFTC[B3:B0] registers
//之前版本的EPxGPIFTCH/L寄存器已经被GPIFTC[B3:B0]寄存器所代替
//EP4 and EP8 are not used in this implementation...此处并未使用EP4和EP8端点
EP1OUTCFG= 0xA0;
SYNCDELAY;
EP1INCFG= 0xA0;
SYNCDELAY;
EP2CFG= 0xAA; //out 512/1024bytes, 2x, bulk；把其中的b5/b4位（TYPE1/TYPE0）设置为10则为批量传输模式
SYNCDELAY;
EP6CFG= 0xEA; // in 512/1024bytes, 2x, bulk
SYNCDELAY;
EP4CFG= 0x02; //clear valid bit
SYNCDELAY;
EP8CFG= 0x02; //clear valid bit
SYNCDELAY;
// FIFORESET是用于FIFO状态复位的
FIFORESET= 0x80; // activate NAK-ALLto avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET= 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET= 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET= 0x06; // reset, FIFO 6
SYNCDELAY;
FIFORESET= 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET= 0x00; // deactivate NAK-ALL
SYNCDELAY;
//handle the case where we were already in AUTO mode...设置EP2为自动输出16位模式
//...for example: back to back firmware downloads...设置EP6为自动输入16位模式
/*EP2BCL= 0x80; // arm EP2OUT bywriting byte count w/skip.
SYNCDELAY;
EP2BCL= 0x80; // arm EP2OUT bywriting byte count w/skip.
SYNCDELAY;
OUTPKTEND= 0x82; // Arm both EP2 buffers toPrime the pum
SYNCDELAY;
OUTPKTEND= 0x82; // Arm both EP2 buffers toPrime the pum
SYNCDELAY;
//core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP2FIFOCFG= 0x00; // AUTOOUT=0,WORDWIDE=1
SYNCDELAY; //
EP2FIFOCFG= 0x10; // AUTOOUT=1,WORDWIDE=1
SYNCDELAY;*/
//若 IN 数据缓冲区数据不满足传输数据包大小要求，如IN批量传输包为 1024，
//若缓冲区大小数据为 10 字节，可通过INPKTEND 来提交
//INPKTEND= 0x84; // Arm both EP6 buffers toPrime the pum
//SYNCDELAY;
//INPKTEND= 0x84; // Arm both EP6 buffers toPrime the pum
//SYNCDELAY;
EP6FIFOCFG= 0x00;
SYNCDELAY; //
EP6FIFOCFG= 0x08; // AUTOIN=1,ZEROLENIN=1, WORDWIDE=0(8BIT)
SYNCDELAY; //
EP6BCH = 0x03; // arm EP6OUT by writing bytecount w/skip.
SYNCDELAY;
EP6BCL = 0xC0; // arm EP6OUT by writing bytecount w/skip.
SYNCDELAY;
EP6BCH = 0x03; // arm EP6OUT by writing bytecount w/skip.
SYNCDELAY;
EP6BCL = 0xC0; // arm EP6OUT by writing bytecount w/skip.
SYNCDELAY;/**/
FIFOPINPOLAR= 0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;
EP6AUTOINLENH = 0x03; // EZ-USBautomatically commits data in 512-byte chunks03
SYNCDELAY;
EP6AUTOINLENL = 0xC0; //c0
SYNCDELAY;
//JTAG Enable and SYNC signals for ZTEXSpartan 6 module 1.1 (FGPA+FX2LP setup)？？？什么作用,FX2LP与ZTEX的端口连接
PORTACFG&= 0xFD;
SYNCDELAY;
OEA|=0x02;//Declare PA.1 as output... SLWR
SYNCDELAY;
IOA|=0x02;//output 1 on PA.1
SYNCDELAY;
//OEC&=0x01;//PC.0 as output (SYNC signal)PC.0为同步信号
//SYNCDELAY;
//IOC|=0x00;//output 0 on PC.0...SYNC signal is LOW
//SYNCDELAY;
OED&=0xFE;//PD.0 as input (Clock changing signal)PD.0为内部与外部时钟切换信号
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
PORTACFG &= 0x7F;
SYNCDELAY;
OEA |= 0x80; //使PA7为输出口,PA7接SLWR写有效信号
SYNCDELAY;
IOA &=0x7F; //使PA7置0
SYNCDELAY;
//IOA|= 0x80;
//SYNCDELAY;
//Configure for external interrupts
PORTACFG|= 0x01; //配置PORTA PA0为INT0
SYNCDELAY;
TCON|=0x01; //INT0在下降沿有效
SYNCDELAY;
IE|= 0x81; //全局中断使能,INT0中断使能
SYNCDELAY;
}
void TD_Poll( void )
{ // Called repeatedly while the device isidle
if(IOD & 0x01)
{
done_frm_fpga =1;
}
if ((done_frm_fpga)&& (IOD & 0x01)) //当PC.1输入为低电平时，切换到外部时钟输入，且置PC.0(同步信号)为高
{
//IFCONFIG =0x63; //external clock input, Slave FIFOinterface
//SYNCDELAY;
PORTACFG &=0xFD;
SYNCDELAY;
OEA |= 0x02;
SYNCDELAY;
IOA &=0xFD;//output 1 on PA.1...SLWR signal is HIGH
SYNCDELAY;
done_frm_fpga =0;
}
if(!(EP2468STAT &bmEP6FULL)) //ENDPOINT6 FIFO满
{
FIFORESET= 0x80; // activate NAK-ALLto avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET =0x06; // reset, FIFO 6
SYNCDELAY;
FIFORESET =0x00; // deactivate NAK-ALL
SYNCDELAY; /**/
EP6BCH = 0x03; // arm EP6OUT by writing bytecount w/skip.
SYNCDELAY;
EP6BCL =0xC0; // arm EP6OUT bywriting byte count w/skip.
SYNCDELAY;
EP6BCH =0x03; // arm EP6OUT bywriting byte count w/skip.
SYNCDELAY;
EP6BCL =0xC0; // arm EP6OUT bywriting byte count w/skip.
SYNCDELAY;
EP6AUTOINLENH = 0x03; // EZ-USBautomatically commits data in 512-byte chunks03
SYNCDELAY;
EP6AUTOINLENL =0xC0; //c0
SYNCDELAY;
}
INTSETUP &= ~bmAV4EN; // Disable INT4 autovectoring so that weuse the external INT4
}
