Moore有限状态机(finite state machine,FSM)中,电路的输出取决于机器的状态而与其输入无关。
1 moudule MooreFSM(sel, clk, z_out); 2 input sel, clk; 3 output z_out; 4 reg z_out; 5 6 parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3; 7 reg [1:0] mooreState; 8 9 always@(posedge clk) 10 case(mooreState) 11 S0:begin 12 z_out <= 1; 13 mooreState <= (!sel)?S0:S2; 14 end 15 S1:begin 16 z_out <= 0; 17 mooreState <= (!sel)?S0:S2; 18 end 19 S2:begin 20 z_out <= 0; 21 mooreState <= (!sel)?S2:S3; 22 end 23 S3:begin 24 z_out <= 1; 25 mooreState <= (!sel)?S1:S3; 26 end 27 endcase 28 endmodule