项目名称

序列检测

具体要求：

1. 检测序列：0010
2. 检测出序列之后发出同步高脉冲，若输入序列出现0010010则输出两个同步高脉冲

设计架构

clk:时钟信号

rst_n:复位信号

flow:输入序列

flag:检测出来脉冲标志信号

状态转移图

代码设计

verilog程序实现

module flow_check(
	input			clk,
	input			rst_n,
	input			flow,
	output  reg     flag
);

reg [2:0] state;
localparam s0=3'd0;
localparam s1=3'd1;
localparam s2=3'd2;
localparam s3=3'd3;
localparam s4=3'd4;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		begin
			state<=s0;
			flag<=0;
		end
	else begin
		case(state)
			s0:begin //检测第一个0
					if(flow==0)
						state<=s1;
					else
						state<=s0;
				end
			s1:begin //检测 第二个0
					if(flow==0)
						state<=s2;
					else
						state<=s0;
				end
			s2:begin //检测1
					if(flow==1)
						state<=s3;
					else
						state<=s2;
				end
			s3:begin //检测第三0
					if(flow==0)
						begin
							state<=s4;
							flag<=1;
						end
					else
						state<=s0;
				end
			s4:begin
					if(flow==0)
						begin
							state<=s2;
							flag<=0;
						end
					else
						begin
							state<=s0;
							flag<=0;
						end
				end
			default:state<=s0;
		endcase
	end

endmodule

仿真代码

`timescale 1ns/1ns
module flow_check_tb;
	reg			clk;
	reg			rst_n;
	reg			flow;
	wire        flag;
flow_check  flow_check(
	.clk(clk),
	.rst_n(rst_n),
	.flow(flow),
	.flag(flag)
);

initial clk=0;
always #10 clk=~clk;

initial begin
	rst_n=0;
	flow=0;
	#200.1
	rst_n=1;
	
	#10
	flow={$random}%2;
	forever begin //一直执行
		#20
		flow={$random}%2;
	end
end
//-----------------------//
//上电2000ns后停止仿真
initial begin
	#20000
	$stop;
end

endmodule

仿真结果

从图中可以看出输入0010010之后输出两个高脉冲标志