文章目录
前言
显示系统任务主要用于显示信息和调试信息,从日志文件中跟踪仿真的流程,也有助于更快地进行调试。显示任务有不同的组别和格式,它们可以打印数值。
仿真可不是只有波形就完事无忧的,有的时候需要一些显示任务将某些节点的数据打印出来,有利于分析。
如下格式语句一定见过吧:
$monitor ("[$monitor] time=%0t a=0x%0h b=0x%0h", $time, a, b);
$display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b);
类似的东西都很常见,这里一起学习下吧。
正文
Display/Write Tasks
$display
和$write
都会按照参数列表中的顺序显示参数。
$display(<list_of_arguments>);
$write(<list_of_arguments>);
$write
不会在字符串末尾添加换行符,而$display
会,从下面的例子可以看出。
module tb;
initial begin
$display ("This ends with a new line ");
$write ("This does not,");
$write ("like this. To start new line, use newline char
");
$display ("This always start on a new line !");
end
endmodule
This ends with a new line
This does not,like this. To start new line, use newline char
Hi there !
Verilog Strobes
display类似。
module tb;
initial begin
reg [7:0] a;
reg [7:0] b;
a = 8'h2D;
b = 8'h2D;
#10; // Wait till simulation reaches 10ns
b <= a + 1; // Assign a+1 value to b
$display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b);
$strobe ("[$strobe] time=%0t a=0x%0h b=0x%0h", $time, a, b);
#1;
$display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b);
$strobe ("[$strobe] time=%0t a=0x%0h b=0x%0h", $time, a, b);
end
endmodule
需要注意的是,$strobe
在时间10ns显示变量b的最终更新值,也就是0x2E,而$display
只有在11ns的下一次模拟delta中才会接收到这个值。
[$display] time=10 a=0x2d b=0x2d
[$strobe] time=10 a=0x2d b=0x2e
[$display] time=11 a=0x2d b=0x2e
[$strobe] time=11 a=0x2d b=0x2e
Verilog Continuous Monitors
每当参数列表中的变量或表达式发生变化时,$monitor
就会自动打印出变量或表达式的值。它达到的效果与每次更新参数后调用$display
类似。
module tb;
initial begin
reg [7:0] a;
reg [7:0] b;
a = 8'h2D;
b = 8'h2D;
#10; // Wait till simulation reaches 10ns
b <= a + 1; // Assign a+1 value to b
$monitor ("[$monitor] time=%0t a=0x%0h b=0x%0h", $time, a, b);
#1 b <= 8'hA4;
#5 b <= a - 8'h33;
#10 b <= 8'h1;
end
endmodule
请注意, monitor任务可以在仿真过程中任意多次发出。
[$monitor] time=10 a=0x2d b=0x2e
[$monitor] time=11 a=0x2d b=0xa4
[$monitor] time=16 a=0x2d b=0xfa
[$monitor] time=26 a=0x2d b=0x1
Verilog Format Specifiers
为了在显示函数中打印变量,必须为每个变量给出适当的格式指定符。
Argument | Description |
---|---|
%h, %H | Display in hexadecimal format |
%d, %D | Display in decimal format |
%b, %B | Display in binary format |
%m, %M | Display hierarchical name |
%s, %S | Display as a string |
%t, %T | Display in time format |
%f, %F | Display ‘real’ in a decimal format |
%e, %E | Display ‘real’ in an exponential format |
module tb;
initial begin
reg [7:0] a;
reg [39:0] str = "Hello";
time cur_time;
real float_pt;
a = 8'h0E;
float_pt = 3.142;
$display ("a = %h", a);
$display ("a = %d", a);
$display ("a = %b", a);
$display ("str = %s", str);
#200 cur_time = $time;
$display ("time = %t", cur_time);
$display ("float_pt = %f", float_pt);
$display ("float_pt = %e", float_pt);
end
endmodule
a = 0e
a = 14
a = 00001110
str = Hello
time = 200
float_pt = 3.142000
float_pt = 3.142000e+00
Verilog Escape Sequences
有些字符被认为是特殊字符,因为它们代表其他显示目的,如换行、制表符和换页。为了打印这些特殊字符,必须对这些字符的每次出现进行转义。
Argument | Description |
---|---|
\n | New line character |
\t | Tab character |
\ | The \ character |
" | The " character |
%% | The % character |
module tb;
initial begin
$write ("Newline character \n");
$display ("Tab character \tstop");
$display ("Escaping " %%");
/*
// Compilation errors
$display ("Without escaping "); // ERROR : Unterminated string
$display ("Without escaping ""); // ERROR : Unterminated string
*/
end
endmodule
Newline character
Tab character stop
Escaping " %
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