Perl源代码
#!/user/bin/perl -w
use strict;
use POSIX;
my $cur_time = strftime("%m/%d/%Y",localtime());#print $cur_time."\n";
my $file_name;
my $module_name;
my $author_name = "Sniper";
my $tab = " "x4;
if(@ARGV == 1)
{
$file_name = $ARGV[0]. "\.v";
$module_name = $ARGV[0];
}
else
{
&help_message();
}
open(LOG,">",$file_name) or die "Can not open $file_name for writting!\n";
my $str = "";
$str .= "`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: $cur_time
// Design Name: $author_name
// Module Name: $module_name
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////";
$str .= "
module $module_name(
input clk,
input rst_n,
input [7:0] Din,
output reg [7:0] Dout
);
//reg
//wire
//assign
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
Dout[7:0] <= 8'h00;
else
Dout[7:0] <= Din[7:0];
end
always@(*)
begin
end
endmodule
";
print LOG $str;
close (LOG);
print "The file $file_name has been generated!\n\n";
sub help_message
{
print "\n\nTHe $0 script used to generate a verilog source file.\n\n";
print "Usage: perl $0 file_name\n\n";
print "Example: perl $0 top\n";
print "-"x60 . "\n\n";
exit;
}
运行结果