\qquad 下面是HD-GR GNSS导航软件的射频前端设置功能实现代码:
// spi_max2769.c -- RF front end setting functions.
/*
* Copyright (C) 2005 Andrew Greenberg
* Distributed under the GNU GENERAL PUBLIC LICENSE (GPL) Version 2 (June 1991).
* See the "COPYING" file distributed with this software for more information.
*/
/*
* HD-GR GNSS receiver project
* Modes : None
* version : V1.0
* date : xx/xx/2015
*/
#include <io.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include "includes.h"
#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "alt_types.h"
#include "altera_avalon_spi.h"
#include "spi_max2769.h"
//#define spi_max2769_2_config_GPS_L1
#define spi_max2769_2_config_lna_off
#ifdef spi_max2769_2_config_GPS_L1
// max2769 spi config for GPS L1
alt_u32 spi_max2769_config[10] = {
#ifdef spi_max2769_2_config_lna_off
MAX2769_CONF1_LNAOFF,
#else
MAX2769_CONF1_NORMAL, // CONF1 // 0xA2919A3
#endif // spi_max2769_config_lnamode_off
0x0550288, // CONF2 // 0x0550288
0xEAFE1DC, // CONF3 // 0xEAFF1DC
0x9EC0008, // PLLCONF // 0x9EC0008
0x0C00080, // DIV, // 0x0C00080 (GPS)
0x8000070, // FDIV // 0x8000070
0x8000000, // STRM // 0x8000000
0x10061B2, // CLK // 0x10061B2
0x1E0F401, // TEST1 // 0x1E0F401
0x14C0402};// TEST2 // 0x14C0402
#else
//max2769 spi config for BD B1
alt_u32 spi_max2769_config[10] = {
#ifdef spi_max2769_2_config_lna_off
MAX2769_CONF1_LNAOFF,
#else
MAX2769_CONF1_NORMAL, // CONF1 // 0xA2919A3
#endif // spi_max2769_config_lnamode_off
0x055028C, // CONF2
0xEAFE1DC, // CONF3
0x9EC0008, // PLLCONF
0x0BE4080, // DIV,BD1:0x0BE4080
0x0000070, // FDIV,L1和BD1:0x00000705
0x8000000, // STRM
0x10061B2, // CLK
0x1E0F401, // TEST1
0x14C0402}; // TEST2
#endif // spi_max2769_2_config_GPS_L1
void spi_max2769_2_init(void)
{
// 设置SPI的control寄存器: 0xc0即bit6=1, bit7=1
// bit6 ITRDY置1则为发送就绪状态使能中断
// bit7 IRRDY置1则为接收就绪状态使能中断
IOWR_32DIRECT(SPI_MAX2769_2_BASE, 12, 0xc0);
// SPI的status寄存器清零: 0x60即bit5=0, bit6=0
// bit5 TMT 传输移位寄存器空标志。(主机模式下)当TMT=0时表示一次传输
// 正在进行。TMT=1表示移位寄存器空。
// bit6 TRDY发送等待。TRDY=1表示txdata寄存器空,可以发起新的一次写入。
IOWR_32DIRECT(SPI_MAX2769_2_BASE, 8, 0x60);
}
void spi_max2769_2_write(alt_u8 addr, alt_u32 cfg)
{
alt_u8 wdata[4];
wdata[0] = (cfg >> 20) & 0xFF;
wdata[1] = (cfg >> 12) & 0xFF;
wdata[2] = (cfg >> 4) & 0xFF;
wdata[3] = ((cfg << 4) & 0xF0) | (addr & 0x0F);
alt_avalon_spi_command(SPI_MAX2769_2_BASE, 0, 4, wdata, 0, 0, 0);
}
void spi_max2769_2_setup(void)
{
alt_u8 addr;
for (addr = 0; addr < 10; addr ++) {
spi_max2769_2_write(addr, spi_max2769_config[addr]);
}
}