Asynchronous Clock Conversion
两种情形:
Situation 1:主时钟频率245.76MHz,脉冲A由主时钟产生。采样时钟为122.88MHz,需要在采样时钟下正确采集脉冲A。
采用打两拍传递的方法进行采样。
Situation 2:主时钟频率122.88MHz,脉冲A由主时钟产生。采样时钟为245.76MHz,需要在采样时钟下正确采集脉冲A。
通过采集脉冲沿的方法来进行采样。
代码块:
'timescale 1ns/1ps
module ACC_mode1(
clka,clkb,rst,pulse_a,pulse_b,Sig
);
input clka,clkb;
input rst;
input pulse_a;
output reg pulse_b;
reg [1:0] Sig;
always@(posedge clka) begin
if(rst)
Sig <= 0;
else if(pulse_a == 1)
Sig <= 1;
else if(pulse_b == 1)
Sig <= 0;
else
Sig <= Sig;
end
always@(posedge clkb) begin
if(Sig)
pulse_b <= 1;
else
pulse_b <= 0;
end
endmodule
TestBench:
module TB_ACC_mode1;
reg clka,clkb;
reg rst;
reg pulse_a;
wire pulse_b;
reg Sig;
reg [1:0] cnt;
wire pulse_cnt;
initial begin
clka = 1;
clkb = 1;
rst = 1;
cnt = 0;
#4.069;
rst = 0;
#4.069;
cnt = 1;
#4.069;
cnt = 0;
end
always begin
#2.048 clka = ~clka;
end
always begin
#4.069 clkb = ~clkb;
end
always@(posedge clka) begin
if(rst)
pulse_a <= 0;
else if(cnt == 1)
pulse_a <= 1;
else
pulse_a <= 0;
end
assign pulse_cnt = pulse_a;
ACC_mode1 u1(
XXXXXXXX
);
endmodule
预期波形:
'timescale 1ns/1ps
module ACC_mode2(
clka,clkb,rst,pulse_a,pulse_b,delay
);
input clka,clkb;
input rst;
input pulse_a;
output pulse_b;
reg [2:0] delay;
reg [2:0] Sig;
always@(posedge clka) begin
if(rst)
delay <= 3'b000;
else
delay <= {
delay[1:0],pulse_a};
end
always@(posedge clkb) begin
if(rst)
Sig <= 0;
else
Sig <= = {
~delay[2]} && delay[1];
end
assign pulse_b = Sig;
endmodule
TestBench:
module TB_ACC_mode2;
reg clka,clkb;
reg rst;
reg pulse_a;
wire pulse_b;
reg [1:0] cnt;
initial begin
clka = 1;
clkb = 1;
rst = 1;
cnt = 0;
#8.138;
rst = 0;
#8.138;
cnt = 1;
#8.138;
cnt = 0;
end
always begin
#4.069 clka = ~clka;
end
always begin
#2.048 clkb = ~clkb;
end
always@(posedge clka) begin
if(rst)
pulse_a <= 0;
else if(cnt == 1)
pulse_a <= 1;
else
pulse_a <= 0;
end
/*ACC_mode2 u2(
clka,clkb,rst,pulse_a,pulse_b,delay
);*/
endmodule
预期波形: