本文主要记录MATLAB HDL Coder的入门学习和使用过程
MATLAB HDL
Name
MATLAB HDL
Description
This repository documents how to use MATLAB’s Simulink’s HDL tools to accelerate HDL-related work.
Installation
module load matlab/R2022a
Steps
First go through initial steps. Then look around advanced steps.
name in grey
basically means click a button with a greyed name.
Inital steps
-
Create a directory as your work space, such as “hdl_coder”.
-
Run commands:
cd <your dir>
andmatlab
. -
Click
Simulink
-
Create a
Blank Model
if starting from scratch. Else choose others. -
Save
this model with a desired file name. -
Add blocks. Click
Library Browser
or double-click blank area in the canvas. -
Select functional blocks from “HDL Coder”
-
Add functional blocks by right-click -> Add block to model <xxx>.
-
Add input and output ports via “Ports & Subsystems” or “Sinks” or “Sources” class.
-
Connect IOs of each block by wire.
-
Click App -> HDL Coder
-
Now specify configurations
- Click
Settings
->HDL Code Generation Settings
- In “HDL Code Generation”, set “Language” as “Verilog”, set “Folder” as “<your model path>/hdlsrc”.
Hardware Implementation
-> set “Device Vendor” as “ASIC/FPGA”. (If doing ASIC/FPGA Implementation)Global Settings
-> Clock settings -> Reset type -> Choose “Synchronous”.Apply
andOK
.
- Click
-
In the “HDL CODE” tab, click
Generate HDL Code
. -
If there is an error:
For the block ‘xxx’
Signals of type ‘Double’ will not generate synthesizable HDL. For synthesizable HDL code, set the “Library” option to “Native Floating Point”. For non-synthesizable and simulation-only HDL code, set the “Check for presence of reals in generated HDL code” diagnostic to “Warning” or “None”.Double-click all inports one by one ->
Signal Attributes
-> change “Data type” to something other than “double”. -
Generate HDL Code
. Get .v
Simulation
-
Click wires of interest, hover mouse to “Log Selected Singal”, click.
-
Select desired sources.
-
In “SIMULATION” tab -> “SIMULATE” area, click
Run
. -
If there is an error related to variable-step or fixed-step, change
Settings
-> “Solver” -> “Solver selection” -> “Type” to “Fixed-step” -
In “SIMULATION” tab -> “REVIEW RESULTS” area, click
Data Inspector
orLogic Analyzer
.
Advanced steps
- Change inports’
Singal Attributes
-> “Port Dimension” to do vector operation. - Add blocks of “subsystem” to achieve hierarchy. This is also useful when wanting one specific component’s Verilog code.
- Simulation’s stimulation data import.
Settings
-> “Data Import/Export” -> “Input” -> type the structure or time series - Automation commands:
open_system("xxx")
out=sim("xxx")
logsout=out.logsout
logsout.get(<n>).Values.<values of interest>
Contributing
Help me with automating all aforementioned processes, meaning, find equivalent MATLAB commands for them.
Project status
Ongoing
Errors & solutions:
Here documented common errors and their solutions.
-
Error:
For the block ‘xxx/Divider’ Product block with divide input (/) only supports Saturation “On”.
Solution: In
Signal Attributes
-> tick “Sarutate on integer overflow” and choose “Integer rounding mode” to be “Simplest” or “Zero”. -
Cannot generate code for Sqrt:
Solution: change Sqrt’s output type as fixed points. No need to change the floating point library in configuration. Keep “None”.
-
Cannot generate code for Exp:
Solution: add a data type converter to convert FX to FP. -
Simulation’s stimulations do not match workspace’s time and value:
Solution:Settings
-> “Solver” -> “Solver selection” -> “Type” := “Fixed-step” , “Solver” := “discrete (no continuous states)” & “Solver details” -> “Fixed-step size” := unit time frame that you set in the workspace or timetable