.ucf 配置文件 不变,适用于下面几个代码
.ucf 配置文件 不变,适用于下面几个代码
NET "ext_clk_25m" LOC=P23 | IOSTANDARD = LVCMOS33;
NET "ext_rst_n" LOC=P24 | IOSTANDARD = LVCMOS33;
NET "led[0]" LOC=P17 | IOSTANDARD = LVCMOS33;
NET "led[1]" LOC=P16 | IOSTANDARD = LVCMOS33;
NET "led[2]" LOC=P15 | IOSTANDARD = LVCMOS33;
NET "led[3]" LOC=P14 | IOSTANDARD = LVCMOS33;
NET "led[4]" LOC=P12 | IOSTANDARD = LVCMOS33;
NET "led[5]" LOC=P11 | IOSTANDARD = LVCMOS33;
NET "led[6]" LOC=P10 | IOSTANDARD = LVCMOS33;
NET "led[7]" LOC=P9 | IOSTANDARD = LVCMOS33;
Verilog 计数器 用8个LED 代表 0 ~ 255
.v 文件
//8个LED循环点亮,实现流水灯效果
module sp6(
input ext_clk_25m,//外部输入25MHz时钟信号
input ext_rst_n, //外部输入复位信号,低电平有效
output reg[7:0] led//8个LED指示灯接口
);
reg[23:0] cnt;//20位计数器
//24bit cnt计数器进行循环计数,最大计数为0xff_ff_ff
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
cnt <= 20'd0;
else
cnt <= cnt+1'b1;
//计数器cnt计数到最大值时,切换点亮的指示灯
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
led <= 8'b1111_1111; //初始状态全部高电平,LED都不亮
else if(cnt == 20'hff_ff_ff)
led <= led - 1'b1; //将会看到 LED亮灭代表 0~255
else
;
endmodule
流水灯,位拼接运算符,实现移位操作
位拼接运算符,实现移位操作
//8个LED循环点亮,实现流水灯效果
module sp6(
input ext_clk_25m,//外部输入25MHz时钟信号
input ext_rst_n, //外部输入复位信号,低电平有效
output reg[7:0] led//8个LED指示灯接口
);
reg[23:0] cnt;//20位计数器
//24bit cnt计数器进行循环计数,最大计数为0xff_ff_ff
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
cnt <= 20'd0;
else
cnt <= cnt+1'b1;
//计数器cnt计数到最大值时,切换点亮的指示灯
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
led <= 8'b1111_1010; //初始状态全部高电平,LED都不亮
else if(cnt == 20'hff_ff_ff)
led <= {led[6:0],led[7]}; //位拼接运算符
//led <= {led[6],led[5],led[4],led[3],led[2],led[1],led[0],led[7]}; //位拼接运算法展开写,效果一样
else
;
endmodule
流水灯也可以这样:
流水灯也可以这样:
//8个LED循环点亮,实现流水灯效果
module sp6(
input ext_clk_25m,//外部输入25MHz时钟信号
input ext_rst_n, //外部输入复位信号,低电平有效
output reg[7:0] led//8个LED指示灯接口
);
reg[23:0] cnt;//20位计数器
//24bit cnt计数器进行循环计数,最大计数为0xff_ff_ff
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
cnt <= 20'd0;
else
cnt <= cnt+1'b1;
//计数器cnt计数到最大值时,切换点亮的指示灯
always @ (posedge ext_clk_25m or negedge ext_rst_n)
if(!ext_rst_n)
led <= 8'b1111_1110; //初始状态全部高电平,LED都不亮
else if(cnt == 20'hff_ff_ff)
begin
led[0] <= led[1]; //位拼接运算符
led[1] <= led[2]; //位拼接运算符
led[2] <= led[3]; //位拼接运算符
led[3] <= led[4]; //位拼接运算符
led[4] <= led[5]; //位拼接运算符
led[5] <= led[6]; //位拼接运算符
led[6] <= led[0]; //位拼接运算符
end
endmodule