目录
先给出总体示意图：
1、周期（PERIOD）约束
周期约束之前也写过一篇：时序约束之周期约束
时钟周期估计
在进行Period约束之前，需要对电路的时钟周期进行估计，不要过松或过紧的约束。
设计的内部电路所能达到的最高运行频率取决于同步元件本身的建立保持时间，以及同步元件之间的逻辑和布线延迟。
如下图的电路及其时钟周期估计：
编辑约束
对于周期约束可使用Xilinx约束编辑器（Xilinx Constraints Editor），也可以自己编写约束文档。
如果自己编写约束文档，见博文：时序约束之周期约束
时钟偏斜计算
时钟偏斜（clock skew）的具体计算实例，例子中的DCM代表数字时钟管理器：
基本时序报告
数字时钟管理器的周期约束
解释下上面的对时钟输入端进行约束的语句：
下面这段话来自于我的另外一篇博文：时序约束之周期约束
先看下TIMESPEC的用法：
用TIMESPEC 约束定义时钟的方法： 首先在时钟网络 clk 上附加 TNM_NET约束，把clk驱动的所有同步元件定义成一个分组，命名为 “sys_clk ”。
NET “clk” TNM_NET = “sys_clk”
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 50ns HIGH 20ns
用TIMESPEC 约束定义的识别符 TS_sys_clk可以被其他时钟定义引用，这对于需要派生时钟的场合十分适用。
如果还是不明白，还可以看官方文档：Constraints Guide
摘出来一段吧：
TIMESPEC Period Method UCF Syntax
The following constraint is defined using the TIMESPEC keyword in conjunction with a TNM constraint attached to the relevant clock net.语法如下：
TIMESPEC “TSidentifier ”=PERIOD “TNM_reference ” period {HIGH | LOW} [high_or_low_time ] INPUT_JITTER value;
• identifier
A reference identifier that has a unique name.
• TNM_reference
Identifies the group of elements to which the period constraint applies. This is typically the name of a TNM_NET that was attached to a clock net, but it can be any TNM group or user group (TIMEGRP) that contains only synchronous elements.（TNM_reference 典型的是 TNM_NET后面的标识符命名，例如：NET “clk” TNM_NET = “sys_clk”，那么TNM_reference就可以取 sys_clk）
The following rules apply:
• The variable name period is the required clock period.
• The default units for period are nanoseconds, but the number can be followed by ps, ns, micro, or ms. The period can also be specified as a frequency value, using units of MHz, GHz, or kHZ.（周期的单位可以指定为频率单位，例如MHz，GHz，或者 kHz）
• Units may be entered with or without a leading space.
• Units are case-insensitive.
• The HIGH|LOW keyword indicates whether the first pulse in the period is high or low, and the optional high_or_low_time is the polarity of the first pulse. This defines the initial clock edge and is used in the OFFSET constraint. HIGH is the default logic level if the logic level is not specified.（The HIGH|LOW 关键词指定第一个脉冲是高还是低，如果未指定，默认为高！）
• If an actual time is specified, it must be less than the period.
• If no high_or_low_time is specified the default duty cycle is 50%.（如果高电平和低电平持续时间没有指定，那么默认占空比为50%！）
• The default units for high_or_low_time is ns, but the number can be followed by % or by ps, ns, micro, or ms to specify an actual time measurement.
• INPUT_JITTER is the random, peak-to-peak jitter on an input clock. The default units are ns.
Clock Phase Period Example
下面这张图暂时放着：等我清晰了再解释。
Hold Calculations
Hold time violation is a violation of the hold time requirement. If the datasheet says the minimum required hold time is 10 ns and you change the data 5 ns after the clock edge, then you have committed a hold time violation and there is no guarantee which data value will end up on the flipflop output.
如果没有达到保持时间的要求，就会出现Hold time violation，同理如果没有满足建立时间的要求，就会出现Setup time violation。
https://electronics.stackexchange.com/questions/29464/what-is-hold-time-violation
http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3b.html
