/*****************************************************************************
*
* $Id$
*
* Copyright (C) 2007-2009 Florian Pose, Ingenieurgemeinschaft IgH
*
* This file is part of the IgH EtherCAT Master.
*
* The IgH EtherCAT Master is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* The IgH EtherCAT Master is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
* Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with the IgH EtherCAT Master; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* ---
*
* The license mentioned above concerns the source code only. Using the
* EtherCAT technology and brand is only permitted in compliance with the
* industrial property and similar rights of Beckhoff Automation GmbH.
*
****************************************************************************/
#include <errno.h>
#include <signal.h>
#include <stdio.h>
#include <string.h>
#include <sys/resource.h>
#include <sys/time.h>
#include <sys/types.h>
#include <unistd.h>
#include <time.h> /* clock_gettime() */
#include <sys/mman.h> /* mlockall() */
#include <malloc.h>
/****************************************************************************/
#include "ecrt.h"
/****************************************************************************/
/** Task period in ns. */
#define PERIOD_NS 2000000
#define CLOCK_TO_USE CLOCK_REALTIME
//#define MEASURE_TIMING
/****************************************************************************/
//#define NSEC_PER_SEC (1000000000L)
//#define PERIOD_NS (NSEC_PER_SEC / FREQUENCY)
/* Constants */
#define NSEC_PER_SEC (2000000000)
#define FREQUENCY (NSEC_PER_SEC / PERIOD_NS)
#define DIFF_NS(A, B) (((B).tv_sec - (A).tv_sec) * NSEC_PER_SEC/2 + \
(B).tv_nsec - (A).tv_nsec)
#define TIMESPEC2NS(T) ((uint64_t) (T).tv_sec * NSEC_PER_SEC/2 + (T).tv_nsec)
/****************************************************************************/
#define MAX_SAFE_STACK (8 * 1024) /* The maximum stack size which is
guranteed safe to access without
faulting */
/****************************************************************************/
// EtherCAT
static ec_master_t *master = NULL;
static ec_master_state_t master_state = {};
static ec_domain_t *domain1 = NULL;
static ec_domain_state_t domain1_state = {};
static ec_slave_config_t *sc_ana_in = NULL;
static ec_slave_config_state_t sc_ana_in_state = {};
/****************************************************************************/
// process data
static uint8_t *domain1_pd = NULL;
#define BusCouplerPos 0, 0
#define Beckhoff_EK1100 477, 271601776
// offsets for PDO entries
static unsigned int off_ana_out_contrl;
static unsigned int off_ana_out_targetpos;
static unsigned int off_ana_out_v;
static unsigned int off_dig_out_ref_v;
static unsigned int off_dig_out_diffv;
static unsigned int off_dig_in_status;
static unsigned int off_dig_out_actual_pos;
const static ec_pdo_entry_reg_t domain1_regs[] = {
/* alias:0 pos:0 venderid: 0x2 pId:0x044c252, index:0x3101 subindex offset:Pointer to a variable to store the PDO entry's */
{BusCouplerPos, Beckhoff_EK1100, 0x6040, 0, &off_ana_out_contrl},
{BusCouplerPos, Beckhoff_EK1100, 0x607a, 0, &off_ana_out_targetpos},
{BusCouplerPos, Beckhoff_EK1100, 0x60ff, 0, &off_ana_out_v},
{BusCouplerPos, Beckhoff_EK1100, 0x60c1, 1, &off_dig_out_ref_v},
{BusCouplerPos, Beckhoff_EK1100, 0x60c1, 2, &off_dig_out_diffv},
{BusCouplerPos, Beckhoff_EK1100, 0x6041, 0, &off_dig_in_status},
{BusCouplerPos, Beckhoff_EK1100, 0x6064, 0, &off_dig_out_actual_pos},
{}
};
static unsigned int counter = 0;
static unsigned int blink = 0;
/*****************************************************************************/
// Analog in --------------------------
static ec_pdo_entry_info_t ek1000_pdo_entries[] = {
/* index subindex len*/
{0x6040, 0, 16}, // channel 1 status
{0x607a, 0, 32}, // channel 1 value
{0x60ff, 0, 32}, // channel 2 status
{0x60c1, 1, 32}, // channel 2 value
{0x60c1, 2, 16}, // channel 1 value (alt.)
{0x6041, 0, 16}, // channel 1 value (alt.)
{0x6064, 0, 32}, // channel 1 value (alt.)
};
static ec_pdo_info_t ek1000_pdos[] = {
/* index n_entries *entries */
{0x1601, 5, ek1000_pdo_entries},
{0x1A01, 2, ek1000_pdo_entries + 5}
};
static ec_sync_info_t ek1000_syncs[] = {
/*index direction n_pdos */
{2, EC_DIR_OUTPUT, 1, ek1000_pdos},
{3, EC_DIR_INPUT,1, ek1000_pdos + 1},
{0xff}
};
static unsigned int sync_ref_counter = 0;
const struct timespec cycletime = {0, PERIOD_NS};
/*****************************************************************************/
struct timespec timespec_add(struct timespec time1, struct timespec time2)
{
struct timespec result;
if ((time1.tv_nsec + time2.tv_nsec) >= NSEC_PER_SEC/2) {
result.tv_sec = time1.tv_sec + time2.tv_sec + 1;
result.tv_nsec = time1.tv_nsec + time2.tv_nsec - NSEC_PER_SEC/2;
} else {
result.tv_sec = time1.tv_sec + time2.tv_sec;
result.tv_nsec = time1.tv_nsec + time2.tv_nsec;
}
return result;
}
/*****************************************************************************/
/*****************************************************************************/
void check_domain1_state(void)
{
ec_domain_state_t ds;
ecrt_domain_state(domain1, &ds);
if (ds.working_counter != domain1_state.working_counter) {
printf("Domain1: WC %u.\n", ds.working_counter);
}
if (ds.wc_state != domain1_state.wc_state) {
printf("Domain1: State %u.\n", ds.wc_state);
}
domain1_state = ds;
}
/*****************************************************************************/
void check_master_state(void)
{
ec_master_state_t ms;
ecrt_master_state(master, &ms);
if (ms.slaves_responding != master_state.slaves_responding) {
printf("%u slave(s).\n", ms.slaves_responding);
}
if (ms.al_states != master_state.al_states) {
printf("AL states: 0x%02X.\n", ms.al_states);
}
if (ms.link_up != master_state.link_up) {
printf("Link is %s.\n", ms.link_up ? "up" : "down");
}
master_state = ms;
}
/*****************************************************************************/
void check_slave_config_states(void)
{
ec_slave_config_state_t s;
//s.al_state = 8;
//s.online =1;
//s.operational = 0;
ecrt_slave_config_state(sc_ana_in, &s);
if (s.al_state != sc_ana_in_state.al_state) {
printf("AnaIn: State 0x%02X.\n", s.al_state);
}
if (s.online != sc_ana_in_state.online) {
printf("AnaIn: %s.\n", s.online ? "online" : "offline");
}
if (s.operational != sc_ana_in_state.operational) {
printf("AnaIn: %soperational.\n", s.operational ? "" : "Not ");
}
sc_ana_in_state = s;
}
/*****************************************************************************/
/****************************************************************************/
void cyclic_task()
{
struct timespec wakeupTime, time;
#ifdef MEASURE_TIMING
struct timespec startTime, endTime, lastStartTime = {};
uint32_t period_ns = 0, exec_ns = 0, latency_ns = 0,
latency_min_ns = 0, latency_max_ns = 0,
period_min_ns = 0, period_max_ns = 0,
exec_min_ns = 0, exec_max_ns = 0;
#endif
// get current time
clock_gettime(CLOCK_TO_USE, &wakeupTime);
while(1) {
wakeupTime = timespec_add(wakeupTime, cycletime);
clock_nanosleep(CLOCK_TO_USE, TIMER_ABSTIME, &wakeupTime, NULL);
#ifdef MEASURE_TIMING
clock_gettime(CLOCK_TO_USE, &startTime);
latency_ns = DIFF_NS(wakeupTime, startTime);
period_ns = DIFF_NS(lastStartTime, startTime);
exec_ns = DIFF_NS(lastStartTime, endTime);
lastStartTime = startTime;
if (latency_ns > latency_max_ns) {
latency_max_ns = latency_ns;
}
if (latency_ns < latency_min_ns) {
latency_min_ns = latency_ns;
}
if (period_ns > period_max_ns) {
period_max_ns = period_ns;
}
if (period_ns < period_min_ns) {
period_min_ns = period_ns;
}
if (exec_ns > exec_max_ns) {
exec_max_ns = exec_ns;
}
if (exec_ns < exec_min_ns) {
exec_min_ns = exec_ns;
}
#endif
// receive process data
ecrt_master_receive(master);
ecrt_domain_process(domain1);
// check process data state (optional)
check_domain1_state();
if (counter) {
counter--;
} else { // do this at 1 Hz
counter = FREQUENCY;
// check for master state (optional)
check_master_state();
#ifdef MEASURE_TIMING
// output timing stats
printf("period %10u ... %10u\n",
period_min_ns, period_max_ns);
printf("exec %10u ... %10u\n",
exec_min_ns, exec_max_ns);
printf("latency %10u ... %10u\n",
latency_min_ns, latency_max_ns);
period_max_ns = 0;
period_min_ns = 0xffffffff;
exec_max_ns = 0;
exec_min_ns = 0xffffffff;
latency_max_ns = 0;
latency_min_ns = 0xffffffff;
#endif
// calculate new process data
blink = !blink;
}
// write process data
#if 0
EC_READ_U16(domain1_pd + off_ana_out_contrl);
EC_READ_S32(domain1_pd + off_ana_out_targetpos);
EC_READ_S32(domain1_pd + off_ana_out_v);
EC_READ_S32(domain1_pd + off_dig_out_ref_v);
EC_READ_U16(domain1_pd + off_dig_out_diffv);
#endif
#if 0
EC_WRITE_U16(domain1_pd + off_ana_out_contrl, 6);
EC_WRITE_S32(domain1_pd + off_ana_out_targetpos,5555);
EC_WRITE_S32(domain1_pd + off_ana_out_v,400);
EC_WRITE_S32(domain1_pd + off_dig_out_ref_v,100);
EC_WRITE_U16(domain1_pd + off_dig_out_diffv, 0);
#endif
EC_READ_U16(domain1_pd + off_dig_in_status);
EC_READ_S32(domain1_pd + off_dig_out_actual_pos);
printf("actual position %d:\n", *(int *)(domain1_pd + off_dig_out_actual_pos));
// EC_WRITE_S32(domain1_pd + off_ana_out_targetpos, 100 + *(int *)(domain1_pd + off_dig_out_actual_pos));
#if 0 //8 mode
EC_WRITE_U16(domain1_pd + off_ana_out_contrl, 15);
//EC_WRITE_S32(domain1_pd + off_ana_out_targetpos,5555);
EC_WRITE_S32(domain1_pd + off_ana_out_targetpos, 100 + *(int *)(domain1_pd + off_dig_out_actual_pos));
EC_WRITE_S32(domain1_pd + off_ana_out_v,400);
#endif
EC_WRITE_U16(domain1_pd + off_ana_out_contrl, 15);
EC_WRITE_S32(domain1_pd + off_dig_out_ref_v,100 + *(int *)(domain1_pd + off_dig_out_actual_pos));
EC_WRITE_S32(domain1_pd + off_ana_out_v,400);
// write application time to master
clock_gettime(CLOCK_TO_USE, &time);
ecrt_master_application_time(master, TIMESPEC2NS(time));
if (sync_ref_counter) {
sync_ref_counter--;
} else {
sync_ref_counter = 1; // sync every cycle
ecrt_master_sync_reference_clock(master);
}
ecrt_master_sync_slave_clocks(master);
// send process data
ecrt_domain_queue(domain1);
ecrt_master_send(master);
#ifdef MEASURE_TIMING
clock_gettime(CLOCK_TO_USE, &endTime);
#endif
}
}
#if 0
void cyclic_task_user()
{
// receive process data
ecrt_master_receive(master);
ecrt_domain_process(domain1);
// check process data state
check_domain1_state();
if (counter) {
counter--;
} else { // do this at 1 Hz
counter = FREQUENCY;
// calculate new process data
blink = !blink;
// check for master state (optional)
check_master_state();
// check for slave configuration state(s) (optional)
check_slave_config_states();
}
#if 1
// read process data
EC_WRITE_U16(domain1_pd + off_ana_out_contrl, 6);
EC_WRITE_S32(domain1_pd + off_ana_out_targetpos,5555);
EC_WRITE_S32(domain1_pd + off_ana_out_v,400);
EC_WRITE_S32(domain1_pd + off_dig_out_ref_v,100);
EC_WRITE_U16(domain1_pd + off_dig_out_diffv, 0);
EC_READ_U16(domain1_pd + off_dig_in_status);
EC_READ_S32(domain1_pd + off_dig_out_actual_pos);
//printf();
#endif
#if 1
// write process data
// EC_WRITE_S32(domain1_pd + off_ana_out_v, 400);
#endif
// send process data
ecrt_domain_queue(domain1);
ecrt_master_send(master);
}
#endif
/****************************************************************************/
void stack_prefault(void)
{
unsigned char dummy[MAX_SAFE_STACK];
memset(dummy, 0, MAX_SAFE_STACK);
}
/****************************************************************************/
int main1(int argc, char **argv)
{
ec_slave_config_t *sc;
struct timespec wakeup_time;
int ret = 0;
/* Lock memory */
if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
fprintf(stderr, "Warning: Failed to lock memory: %s\n",
strerror(errno));
}
stack_prefault();
master = ecrt_request_master(0);
if (!master) {
return -1;
}
domain1 = ecrt_master_create_domain(master);
if (!domain1) {
return -1;
}
// Create configuration for bus coupler
sc = ecrt_master_slave_config(master, BusCouplerPos, Beckhoff_EK1100);
if (!sc) {
return -1;
}
if (ecrt_slave_config_pdos(sc, EC_END, ek1000_syncs)) {
fprintf(stderr, "Failed to configure PDOs.\n");
return -1;
}
sc_ana_in = sc;
if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) {
fprintf(stderr, "PDO entry registration failed!\n");
return -1;
}
// configure SYNC signals for this slave
ecrt_slave_config_dc(sc, 0x0700, PERIOD_NS, 4400000, 0, 0);
printf("Activating master...\n");
if (ecrt_master_activate(master)) {
return -1;
}
if (!(domain1_pd = ecrt_domain_data(domain1))) {
return -1;
}
pid_t pid = getpid();
if (setpriority(PRIO_PROCESS, pid, -19))
fprintf(stderr, "Warning: Failed to set priority: %s\n",
strerror(errno));
printf("Starting cyclic function.\n");
cyclic_task();
#if 0 //user
/* Set priority */
pid_t pid = getpid();
if (setpriority(PRIO_PROCESS, pid, -19)) {
fprintf(stderr, "Warning: Failed to set priority: %s\n",
strerror(errno));
}
/* Lock memory */
if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
fprintf(stderr, "Warning: Failed to lock memory: %s\n",
strerror(errno));
}
stack_prefault();
printf("Starting RT task with dt=%u ns.\n", PERIOD_NS);
clock_gettime(CLOCK_MONOTONIC, &wakeup_time);
wakeup_time.tv_sec += 1; /* start in future */
wakeup_time.tv_nsec = 0;
while (1) {
ret = clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME,
&wakeup_time, NULL);
if (ret) {
fprintf(stderr, "clock_nanosleep(): %s\n", strerror(ret));
break;
}
cyclic_task();
wakeup_time.tv_nsec += PERIOD_NS/2;
while (wakeup_time.tv_nsec >= NSEC_PER_SEC/2) {
wakeup_time.tv_nsec -= NSEC_PER_SEC/2;
wakeup_time.tv_sec++;
}
}
#endif
return ret;
}
/****************************************************************************/