if your testbench has a module that is included in the top design, the post-synthesis functional simulation will go wrong.
You should rename the sub-module for the testbench, as the testbench and the top design should not use the same module.
ex.
The top design has a sub-module named crc_tst.v, and the testbench also has the same sub-module named crc_tst.v.
Then the post-synthesis functional simulation will go wrong.
solution.
Rename the crc_tst.v inculded in testbench, using a different name.
Then the simulaiton will be right.