计数器仿真实验 1
1.电路结构RTL设计图:
2.Quartus扫描生成的电路RTL图:
3.Verilog代码:
module counter6(CLK,RST,CNT);
input CLK,RST;
output [2:0]CNT;
reg [2:0]CNT;
always @(posedge CLK)
if(RST)
CNT<=3'b000;
else
begin
CNT<=CNT+1'b1;
if(CNT>=3'b101) CNT<=3'b000;
end
endmodule
4.仿真结果:
计数器仿真实验 2
1.Quartus扫描生成的电路RTL图:
2.Verilog代码:
module counterM(CLK,RST,CNT);
input CLK,RST;
output [3:0]CNT;
reg [3:0]CNT;
reg [3:0]N=4'b0110;
always @(posedge CLK)
if(RST)
begin
CNT<=4'b0000;
end
else
begin
CNT<=CNT+1'b1;
if(CNT>=N)
begin
CNT<=4'b0000;
N<=N+4'b0001;
end
if(N>4'b1001)
begin
N<=4'b0110;
end
end
endmodule
3.仿真结果:
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