module rst_generator
#(parameter DELAY=24'd0 )
(
input clk,
output reg rst
);
reg [23:0] rst_counter;
reg [2:0] rst_state;
localparam RST_IDLE = 3'b001,
RST_WAIT = 3'b010,
RST_DONE = 3'b100;
initial
begin
rst_state <= RST_IDLE;
end
always @ (posedge clk)
begin
case(rst_state)
RST_IDLE:
begin
rst <= 1'b1; //高电平有效
rst_counter <= 24'd0;
rst_state <= RST_WAIT;
end
RST_WAIT:
begin
if(rst_counter < DELAY)
begin
rst_state <= RST_WAIT;
rst_counter <= rst_counter + 24'd1;
end
else
begin
rst_state <= RST_DONE;
rst_counter <= 24'd0;
end
end
RST_DONE:
begin
rst <= 1'b0;
rst_state <= RST_DONE;
end
default rst_state <= RST_IDLE;
endcase
end
endmodule
//顶层模块
rst_generator
#(
.DELAY(24'd128)
)
rst_generator_inst
(
.clk(clk),
.rst(rst)
);