1.题目
2.源码
// *********************************************************************************
// Project Name : Hamming_code
// Email : [email protected]
// Website : https://home.cnblogs.com/u/hqz68/
// Create Time : 2019/12/14
// File Name : Hamming_code.v
// Module Name : Hamming_code
// Abstract :
// editor : sublime text 3
// *********************************************************************************
// Modification History:
// Date By Version Change Description
// -----------------------------------------------------------------------
// 2019/12/14 宏强子 1.0 Original
//
// *********************************************************************************
`timescale 1ns/1ns
module Hamming_code (
//system signals
input sclk ,
input s_rst_n ,
//input
input start ,
input [3:0] data_i ,
//output
output wire [6:0] data_o
);
//========================================================================\
// =========== Define Parameter and Internal signals ===========
//========================================================================/
localparam s0 = 4'd0 ;
localparam s1 = 4'd1 ;
localparam s2 = 4'd2 ;
localparam s3 = 4'd3 ;
reg [3:0] state ;
reg [6:0] data_reg ;
reg bit_6 ;
reg bit_5 ;
reg bit_3 ;
//=============================================================================
//**************************** Main Code *******************************
//=============================================================================
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
state <= s0;
else if (state == s0 & start == 1'b1)
state <= s1;
else if (state == s1)
state <= s2;
else if (state == s2)
state <= s3;
else if (state == s3)
state <= s0;
else
state <= state;
end
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
data_reg <= 7'd0;
else if(state == s1)
data_reg <= {1'b0,1'b0,data_i[3],1'b0,data_i[2],data_i[1],data_i[0]};
else
data_reg <= data_reg;
end
always @ (state) begin
if (state == s1)
bit_6 = data_reg[4] ^ data_reg[2] ^ data_reg[1];
else if (state == s2)
bit_5 = data_reg[4] ^ data_reg[1] ^ data_reg[0];
else if (state == s3)
bit_3 = data_reg[2] ^ data_reg[1] ^ data_reg[0];
else if (state == s0)begin
bit_6 = 1'b0;
bit_5 = 1'b0;
bit_3 = 1'b0;
end
end
assign data_o = (state == s3) ? {bit_6,bit_5,data_reg[4],bit_3,data_reg[2:0]} : 7'd0;
endmodule
3.测试平台
`timescale 1ns/1ns
module tb_sim();
reg sclk ;
reg s_rst_n ;
reg start ;
reg [3:0] data_i ;
wire [6:0] data_o ;
initial begin
sclk =1;
s_rst_n = 0;
start = 0;
data_i = 4'd0;
#100
s_rst_n =1;
#200
start = 1;
data_i = 4'b0101; //对应输出 01000101
#100
start = 0;
end
always #50 sclk = ~ sclk;
Hamming_code Hamming_code_inst(
//system signals
.sclk (sclk ),
.s_rst_n (s_rst_n ),
//input
.start (start ),
.data_i (data_i ),
//output
.data_o (data_o )
);
endmodule
4.仿真波形