实验原理:使用数字系统中常常需要不同类型的分频,对于偶数次分频要求以50%占空比输出的电路是比较容易的额。但却难以同相同设计方式直接获得奇数分频且占空比为50%的电路。
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DIV is
port(CLK :in std_logic;
K_OR,K1,K2:out std_logic);
end;
architecture BHV of DIV is
signal C1,C2: std_logic_vector(2 downto 0);
signal M1,M2: std_logic;
begin
process(CLK,C1) begin
if rising_edge(CLK) then
if(C1="100") then C1<="000";
else C1<=C1+1;
end if;
if(C1="001") then M1<=not M1;
elsif(C1="011") then M1<=not M1;
end if;
end if;
end process;
process(CLK,C2) begin
if falling_edge(CLK) then
if(C2="100") then C2<="000";
else C2<=C2+1;
end if;
if(C2="001") then M2<=not M2;
elsif(C2="011") then M2<=not M2;
end if;
end if;
end process;
K1<=M1; K2<=M2; K_OR<=M1 OR M2;
end BHV;
1.代码分析:
这里面有两个进程,这是第一个进程
process(CLK,C1) begin
if rising_edge(CLK) then
if(C1="100") then C1<="000";
else C1<=C1+1;
end if;
if(C1="001") then M1<=not M1;
elsif(C1="011") then M1<=not M1;
end if;
end if;
end process;