参考手册RM0440.pdf
调试支持（DBG）
46.1概述
STM32G4系列设备基于带有FPU内核的Cortex®-M4构建，其中包含 
用于高级调试功能的硬件扩展。调试扩展允许
内核将在给定的指令提取（断点）或数据访问时停止 
（观察点）。停止时，内核的内部状态和系统的外部状态可能会
被检查。一旦检查完成，就可以还原核心和系统，并
程序执行恢复。
当连接到主​​机并调试主机时，调试器主机将使用调试功能。 
STM32G4系列MCU。
有两个调试接口：
•串口线
•JTAG调试端口
具有FPU内核的Arm®Cortex®-M4提供集成的片上调试支持。它是
包括：
•SWJ-DP：串行线/ JTAG调试端口
•AHP-AP：AHB接入端口
•ITM：仪器跟踪宏单元
•FPB：Flash补丁断点
•DWT：数据监视点触发器
•TPUI：跟踪端口单元接口（在较大的软件包中可用，其中相应的 
引脚已映射）
•ETM：嵌入式跟踪宏单元（仅在更大的STM32G4系列设备上可用 
封装，其中对应的引脚已映射）
它还包括STM32G4系列专用的调试功能：•灵活的调试引脚分配
•MCU调试箱（支持低功耗模式，控制外设时钟等）
注意：有关带FPU的Arm®Cortex®-M4支持的调试功能的更多信息 
内核，请参阅带有FPU-r0p1的Cortex®-M4技术参考手册，以及 
CoreSight设计套件r0p1 TRM（请参见第46.2节：ReferenceArm®文档）。


46.4引脚排列和调试端口引脚
STM32G4系列MCU提供多种封装，其中有不同数量的 
可用的引脚。结果，与引脚可用性相关的某些功能（ETM）可能会有所不同
包之间。

46.15 ETM（嵌入式跟踪宏单元）
46.15.1概述
ETM可以重建程序执行。使用数据跟踪数据
监视点和跟踪（DWT）组件或指令跟踪宏单元（ITM），而 
使用嵌入式跟踪宏单元（ETM）跟踪指令。
ETM将信息作为数据包传输，并由嵌入式资源触发。这些
资源必须独立编程，并且使用 
触发事件寄存器（0xE0041008）。一个事件可能是一个简单的事件（地址匹配
（来自地址比较器）或两个事件之间的逻辑方程式。触发源是
DWT模块的四个比较器之一，可以监视以下事件：
•时钟周期匹配
•数据地址匹配
有关触发资源的更多信息，请参见第46.13节：DWT（数据 
观察点触发器）。
ETM发送的数据包将输出到TPIU（跟踪端口接口单元）。的
TPIU的格式化程序会添加一些额外的数据包（请参阅第46.17节：TPIU（跟踪端口） 
接口单元）），然后将完整的数据包序列输出到调试器主机。
46.15.2信号协议，包类型
Arm®IHI 0014N的第7章ETMv3信号协议中对此部分进行了描述。 
文献。
46.15.3主要ETM寄存器
有关寄存器的更多信息，请参阅Arm®IHI 0014N规范的第3章。
 
表431.主要ETM寄存器
地址寄存器详细信息
0xE0041FB0 ETM锁定访问写0xC5ACCE55解锁对 
其他ETM寄存器。
0xE0041000 ETM控制该寄存器控制ETM的常规操作， 
例如如何启用跟踪。
0xE0041010 ETM状态该寄存器提供有关当前状态的信息 
跟踪和触发逻辑。
0xE0041008 ETM触发事件该寄存器定义控制触发的事件。
0xE004101C ETM跟踪启用 
控制该寄存器定义了选择哪个比较器。
0xE0041020 ETM跟踪使能事件该寄存器定义跟踪使能事件。
0xE0041024 ETM跟踪开始/停止此寄存器定义触发源使用的跟踪 
分别开始和停止跟踪

46.15.4配置举例
要将简单值输出到TPIU：
•配置TPIU并启用I / IO_TRACEN，以在其中分配TRACE I / O。 
STM32G4系列调试配置寄存器
•将0xC5ACCE55写入ETM锁定访问寄存器以解锁对ETM的访问。 
ITM寄存器
•将0x00001D1E写入控制寄存器（配置跟踪）
•将0000406F写入触发事件寄存器（定义触发事件）
•将0000006F写入跟踪启用事件寄存器（定义事件以开始/停止）
•将00000001写入跟踪开始/停止寄存器（启用跟踪）
•将0000191E写入ETM控制寄存器（配置结束）


DS12288.pdf
3.39.2嵌入式跟踪macrocell™
Arm嵌入式跟踪宏单元可提供更大的指令和数据可见性 
通过以很高的速率从 
STM32G474xB / xC / xE器件通过少量ETM引脚连接到外部硬件 
跟踪端口分析器（TPA）设备。实时记录指令和数据流活动
然后格式化，以显示在运行调试器软件的主机上。TPA
硬件可从通用开发工具供应商处购买。
嵌入式跟踪宏单元可与第三方调试器软件工具一起运行。

Reference manualRM0440.pdf
Debug support (DBG)
46.1 Overview
The STM32G4 Series devices are built around a Cortex®-M4 with FPU core which contains 
hardware extensions for advanced debugging features. The debug extensions allow the 
core to be stopped either on a given instruction fetch (breakpoint) or data access 
(watchpoint). When stopped, the core’s internal state and the system’s external state may 
be examined. Once examination is complete, the core and the system may be restored and 
program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the 
STM32G4 Series MCUs.
Two interfaces for debug are available:
• Serial wire
• JTAG debug port
The Arm® Cortex®-M4 with FPU core provides integrated on-chip debug support. It is 
comprised of:
• SWJ-DP: Serial wire / JTAG debug port
• AHP-AP: AHB access port
• ITM: Instrumentation trace macrocell
• FPB: Flash patch breakpoint
• DWT: Data watchpoint trigger
• TPUI: Trace port unit interface (available on larger packages, where the corresponding 
pins are mapped)
• ETM: Embedded Trace Macrocell (available only on STM32G4 Series devices larger 
packages, where the corresponding pins are mapped)
It also includes debug features dedicated to the STM32G4 Series: • Flexible debug pinout assignment
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm® Cortex®-M4 with FPU 
core, refer to the Cortex®-M4 with FPU-r0p1 Technical Reference Manual and to the 
CoreSight Design Kit-r0p1 TRM (see Section 46.2: Reference Arm® documentation).

46.4 Pinout and debug port pins
The STM32G4 Series MCUs are available in various packages with different numbers of 
available pins. As a result, some functionalities (ETM) related to pin availability may differ 
between packages.

46.15 ETM (Embedded trace macrocell)
46.15.1 General description
The ETM enables the reconstruction of program execution. Data are traced using the Data 
Watchpoint and Trace (DWT) component or the Instruction Trace Macrocell (ITM) whereas 
instructions are traced using the Embedded Trace Macrocell (ETM).
The ETM transmits information as packets and is triggered by embedded resources. These 
resources must be programmed independently and the trigger source is selected using the 
Trigger Event Register (0xE0041008). An event could be a simple event (address match 
from an address comparator) or a logic equation between 2 events. The trigger source is 
one of the four comparators of the DWT module, The following events can be monitored:
• Clock cycle matching
• Data address matching
For more informations on the trigger resources refer to Section 46.13: DWT (data 
watchpoint trigger).
The packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit). The 
formatter of the TPIU adds some extra packets (refer to Section 46.17: TPIU (trace port 
interface unit)) and then outputs the complete packet sequence to the debugger host.
46.15.2 Signal protocol, packet types
This part is described in the section 7 ETMv3 Signal Protocol of the Arm® IHI 0014N 
document.
46.15.3 Main ETM registers
For more information on registers refer to the chapter 3 of the Arm® IHI 0014N specification.
 
Table 431. Main ETM registers
Address Register Details
0xE0041FB0 ETM Lock Access Write 0xC5ACCE55 to unlock the write access to the 
other ETM registers.
0xE0041000 ETM Control This register controls the general operation of the ETM, 
for instance how tracing is enabled.
0xE0041010 ETM Status This register provides information about the current status 
of the trace and trigger logic.
0xE0041008 ETM Trigger Event This register defines the event that controls trigger.
0xE004101C ETM Trace Enable 
Control This register defines which comparator is selected.
0xE0041020 ETM Trace Enable Event This register defines the trace enabling event.
0xE0041024 ETM Trace Start/Stop This register defines the traces used by the trigger source 
to start and stop the trace, respectively

46.15.4 Configuration example
To output a simple value to the TPIU:
• Configure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the 
STM32G4 Series debug configuration register
• Write 0xC5ACCE55 to the ETM Lock Access Register to unlock the write access to the 
ITM registers
• Write 0x00001D1E to the control register (configure the trace)
• Write 0000406F to the Trigger Event register (define the trigger event)
• Write 0000006F to the Trace Enable Event register (define an event to start/stop)
• Write 00000001 to the Trace Start/stop register (enable the trace)
• Write 0000191E to the ETM Control Register (end of configuration)

DS12288.pdf
3.39.2 Embedded trace macrocell™
The Arm embedded trace macrocell provides a greater visibility of the instruction and data 
flow inside the CPU core by streaming compressed data at a very high rate from the 
STM32G474xB/xC/xE devices through a small number of ETM pins to an external hardware 
trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded 
and then formatted for display on the host computer that runs the debugger software. TPA 
hardware is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third party debugger software tools.