给定的一组语句可以使用repeat构造执行N次。
Syntax
repeat (<number>)
//单一陈述
repeat (<number>) begin
// 多条陈述
end
Example #1
module tb;
initial begin
repeat (5) begin
$display ("Repeat this statement");
end
end
endmodule
Simulation Log
ncsim> run
Repeat this statement
Repeat this statement
Repeat this statement
Repeat this statement
Repeat this statement
ncsim: *W,RNQUIE: Simulation is complete.
repeat循环也可以使用for循环实现,但更为冗长。如果不需要在循环内引用变量i,则repeat循环会更合适。
module tb;
bit clk;
always #10 clk = ~clk;
initial begin
bit [2:0] num = $random;
$display ("[%0t] Repeat loop is going to start with num = %0d", $time, num);
repeat (num) @(posedge clk);
$display ("[%0t] Repeat loop has finished", $time);
$finish;
end
endmodule
参考文献:
【1】https://www.chipverify.com/systemverilog/systemverilog-repeat-loop