数字块之间通常使用总线协议进行通信,例如AMBA AXI、WishBone、OCP等。根据特定协议发送数据的总线主机提供控制信号,告诉从服务器数据包何时有效,是读还是写,以及发送了多少字节的数据。主服务器还发送一个地址,后面跟着要存储在该地址的数据。让我们来看一个快速的示例,其中testbench充当主机,并使用有效的数据约束总线包类对象。
// Burst [ 0 -> 1 byte, 1 -> 2 bytes, 2 -> 3 bytes, 3 -> 4 bytes]
// Length -> max 8 transactions per burst
// 协议希望仅发送第一个地址,从设备应根据burst和length属性计算所有其他地址
class BusTransaction;
rand int m_addr;
rand bit [31:0] m_data;
rand bit [1:0] m_burst; // Size of a single transaction in bytes (4 bytes max)单个事务的大小(以字节为单位)(最多4个字节)
rand bit [2:0] m_length; // Total number of transactions
constraint c_addr { m_addr % 4 == 0; } // Always aligned to 4-byte boundary
function void display(int idx = 0);
$display ("------ Transaction %0d------", idx);
$display (" Addr = 0x%0h", m_addr);
$display (" Data = 0x%0h", m_data);
$display (" Burst = %0d bytes/xfr", m_burst + 1);
$display (" Length = %0d", m_length + 1);
endfunction
endclass
module tb;
int slave_start;
int slave_end;
BusTransaction bt;
// Assume we are targeting a slave with addr range 0x200 to 0x800
initial begin
slave_start = 32'h200;
slave_end = 32'h800;
bt = new;
bt.randomize() with { m_addr >= slave_start;
m_addr < slave_end;
(m_burst + 1) * (m_length + 1) + m_addr < slave_end;
};
bt.display();
end
endmodule
Simulation Log
ncsim> run
------ Transaction 0------
Addr = 0x6e0
Data = 0xbbe5ea58
Burst = 4 bytes/xfr
Length = 5
ncsim: *W,RNQUIE: Simulation is complete.
参考文献:
【1】https://www.chipverify.com/systemverilog/systemverilog-bus-protocol-constraints