library ieee;
use ieee.std_logic_1164.all;
entity led is
port(input:in std_logic_vector(7 downto 0):="ZZZZZZZZ";
	en:in std_logic;
	clock:in std_logic;
	output:out std_logic_vector(7 downto 0):="ZZZZZZZZ"
);
end led;
architecture st of led is
signal i:std_logic_vector(7 downto 0):="ZZZZZZZZ";
begin
process(en,clock)
begin
if (en='1' and clock='0') then--rising_edge(clock)
	i<=input;
else
	i<="ZZZZZZZZ";
end if;
end process;
output<=i;
end st;