reg rstb;
always @ (posedge clk_in or negedge rst_n )begin
if (!rst_n) begin
rstb<=1'b0;
end
else if(czt_en_100m)begin
rstb<=1'b0;
end
else if(addr_din_rd[8:0]==9'd511) begin
rstb<=1'b1;
end
else begin
rstb<=rstb;
end
end
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