使用modelsim编写verilog程序如下：

module digitalclock (clk,reset,hour_g,hour_d,minute_g,minute_d,cout);
  
input         clk,reset;
output[3:0]   hour_g,hour_d,minute_g,minute_d;
output        cout;
reg[3:0]      hour_g,hour_d,minute_g,minute_d;
wire          cout;

always @(posedge clk)
begin
  if(~reset)
        minute_d <= 0;
  else if(minute_d==9)
        minute_d <= 0;
  else 
        minute_d <= minute_d + 1;
end

always @(posedge clk)
begin
  if(~reset)
        minute_g <= 0;
  else if(minute_d==9)
  begin
      if(minute_g==5)
        minute_g <= 0;
      else 
        minute_g <= minute_g + 1;
  end
end

assign cout = ((minute_d==9)&&(minute_g==5))?1:0;

always @(posedge clk)
begin
  if(~reset)
        hour_d <= 0;
  else if(cout)
  begin
      if(hour_d==9)
        hour_d <= 0;
      else if((hour_d==3)&&(hour_g==2))
        hour_d <= 0;
      else
        hour_d <= hour_d + 1;
  end
end

always @(posedge clk)
begin
  if(~reset)
        hour_g <= 0;
  else if(cout)
  begin
      if((hour_d==3)&&(hour_g==2))
        hour_g <= 0;
      else if(hour_d==9)
        hour_d <= hour_d + 1;
  end
end

endmodule

module test;
  
reg clk, reset;
wire[3:0]   hour_g,hour_d,minute_g,minute_d;
wire        cout;
parameter cycle = 100;

digitalclock u1(.clk(clk),
                .reset(reset),
                .hour_g(hour_g),
                .hour_d(hour_d),
                .minute_g(minute_g),
                .minute_d(minute_d),
                .cout(cout));
                
always 
  #(cycle/2)  clk = ~clk;
  
initial
begin
  clk = 0;
  reset = 1;
#305  reset = 0;
#450  reset = 1;
end

endmodule