FPGA设计时钟

一.基本功能

1.具有基本的时钟、分钟、秒钟计时输出口。

2.可以通过inc_m,inc_h控制时钟的分针,时针进行校时。

3.在0点时刻进行报时提醒。

【注:未加显示模块】

二.模块输入输出口的意义

输入 意义 输出 意义
clk 时钟 second_g 秒个位数
rst_n 复位 second_s 秒十位数
inc_hour 时钟校准 minute_g 分个位数
inc_min 分钟校准 minute_s 分十位数
    hour_g 时个位数
    hour_s 时十位数
    high_alarm 零点响铃信号



三.参考源代码
module clock(
clk,
rst_n,
inc_hour,
inc_min,
hour_s,
hour_g,
minute_s,
minute_g,
second_s,
second_g,
high_alarm
);
input clk;
input rst_n;
input inc_hour;
input inc_min;

output [1:0] hour_s;
output [3:0] hour_g;
output [2:0] minute_s;
output [3:0] minute_g;
output [2:0] second_s;
output [3:0] second_g;
output  high_alarm;

reg [1:0] hour_s;
reg [3:0] hour_g;
reg [2:0] minute_s;
reg [3:0] minute_g;
reg [2:0] second_s;
reg [3:0] second_g;

wire count_m;
wire count_h;
wire count_d;
wire high_alarm;

always@(posedge clk)begin
		if(!rst_n)begin
			second_g<=0;
			second_s<=0;
		end
		else if((second_g==9)&&(second_s==5))begin
					second_g<=0;
					second_s<=0;
			  end
			  else if((second_g==9)&&(second_s!=5))begin
							second_g<=0;
							second_s<=second_s+1'b1;
					 end
					 else begin
							second_g<=second_g+1'b1;
					 end
	end

assign count_m = ((second_g==9)&&(second_s==5))? 1'b1:0;
assign count_h = ((minute_g==9)&&(minute_s==5))? 1'b1:0;
assign count_d = ((hour_g==3)&&(hour_s==2))?1'b1:0;

always@(posedge clk)begin
		if(!rst_n)begin
			minute_g<=0;
			minute_s<=0;
		end
		else if(inc_min)begin
					if(count_h)begin
						minute_g<=0;
						minute_s<=0;
					end
					else if(minute_g==9)begin
								minute_g<=0;
								minute_s<=minute_s+1'b1;
							end
						  else begin
								minute_g<=minute_g+1'b1;
						  end
			  end
			  else if(count_h&&count_m)begin
						 minute_g<=0;
						 minute_s<=0;
					  end
					 else if(minute_g==9&&count_m)begin
								minute_g<=0;
								minute_s<=minute_s+1'b1;
							end
						   else if(count_m)begin
									minute_g<=minute_g+1'b1;
								 end
	end
	
always@(posedge clk)begin
		if(!rst_n)begin
			hour_g<=0;
			hour_s<=0;
		end
		else if(inc_hour)begin
					if(count_d)begin
						hour_g<=0;
						hour_s<=0;
					end
					else if(hour_g==9)begin
								hour_g<=0;
								hour_s<=hour_s+1'b1;
							end
						  else begin
								hour_g<=hour_g+1'b1;
						  end
			  end
			  else if(count_h&&count_m&&count_d)begin
						 hour_g<=0;
						 hour_s<=0;
					  end
					 else if(hour_g==9&&count_m&&count_h)begin
								hour_g<=0;
								hour_s<=hour_s+1'b1;
							end
						   else if(count_m&&count_h)begin
									hour_g<=hour_g+1'b1;
								 end
	end
assign high_alarm = (second_g==0)&&(second_s==0)&&(minute_g==0)&&(minute_s==0)&&(hour_g==0)&&(hour_s==0)?1'b1:0;

endmodule
			


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转载自blog.csdn.net/weixin_37603007/article/details/79738094