SystemVerilog中的inside关键字允许检查给定值是否在使用inside短语指定的范围内。 除了用作约束之外,它还可以在if和其他条件语句中使用。
Syntax
<variable> inside {<values or range>}
// Inverted "inside"
!(<variable> inside {<values or range>})
例
m_var inside {4, 7, 9} // Check if m_var is either 4,7 or 9
m_var inside {[10:100]} // Check if m_var is between 10 and 100 inclusive
在条件语句中使用时
在以下示例中,if…else和ternary运算符都使用了内部运算符。 如果m_data的随机值在4到9之间(包括4和9),则标志获得值1。否则,标志获得0。同样,if else块使用相同的运算符并打印显示消息。
module tb;
bit [3:0] m_data;
bit flag;
initial begin
for (int i = 0; i < 10; i++) begin
m_data = $random;
// Used in a ternary operator
flag = m_data inside {[4:9]} ? 1 : 0;
// Used with "if-else" operators
if (m_data inside {[4:9]})
$display ("m_data=%0d INSIDE [4:9], flag=%0d", m_data, flag);
else
$display ("m_data=%0d outside [4:9], flag=%0d", m_data, flag);
end
end
endmodule
Simulation Log
ncsim> run
m_data=4 INSIDE [4:9], flag=1
m_data=1 outside [4:9], flag=0
m_data=9 INSIDE [4:9], flag=1
m_data=3 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
m_data=5 INSIDE [4:9], flag=1
m_data=2 outside [4:9], flag=0
m_data=1 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
ncsim: *W,RNQUIE: Simulation is complete.
用于约束
内部运算符在约束中非常有用,它使代码更短且更具可读性。
class ABC;
rand bit [3:0] m_var;
// Constrain m_var to be either 3,4,5,6 or 7
constraint c_var { m_var inside {[3:7]}; }
endclass
module tb;
initial begin
ABC abc = new();
repeat (5) begin
abc.randomize();
$display("abc.m_var = %0d", abc.m_var);
end
end
endmodule
Simulation Log
ncsim> run
abc.m_var = 7
abc.m_var = 6
abc.m_var = 6
abc.m_var = 3
abc.m_var = 4
ncsim: *W,RNQUIE: Simulation is complete.
class ABC;
rand bit [3:0] m_var;
// Inverted inside: Constrain m_var to be outside 3 to 7
constraint c_var { !(m_var inside {[3:7]}); }
endclass
module tb;
initial begin
ABC abc = new();
repeat (5) begin
abc.randomize();
$display("abc.m_var = %0d", abc.m_var);
end
end
endmodule
Simulation Log
ncsim> run
abc.m_var = 1
abc.m_var = 12
abc.m_var = 0
abc.m_var = 14
abc.m_var = 10
ncsim: *W,RNQUIE: Simulation is complete.
Practical Example
假设我们有一个内存位于地址范围0x4000和0x5FFF之间,该内存被分为两个部分。 第一部分用于存储指令,第二部分用于存储数据。 假设我们要随机分配数据的地址,以使该地址位于内存的数据部分之内,那么我们可以轻松地使用内部运算符。
class Data;
rand bit [15:0] m_addr;
constraint c_addr { m_addr inside {[16'h4000:16'h4fff]}; }
endclass
module tb;
initial begin
Data data = new();
repeat (5) begin
data.randomize();
$display ("addr = 0x%0h", data.m_addr);
end
end
endmodule
Simulation Log
ncsim> run
addr = 0x48ef
addr = 0x463f
addr = 0x4612
addr = 0x4249
addr = 0x4cee
ncsim: *W,RNQUIE: Simulation is complete.
参考文献:
【1】https://www.chipverify.com/systemverilog/systemverilog-constraint-inside