module rom_top(clk,rst,q);

	input clk;
	input rst;
	
	output[7:0]q;
	
	reg [7:0] address;
	
	iprom f1(
	.address(address),
	.clock(clk),
	.q(q)
	);
	
	always@(posedge clk or negedge rst)
	if(!rst)
		address <= 8'd0;
	else
		address <= address + 1'b1;
		
endmodule