1.模二加 就是 异或
2.verilog a=3’b100, 1在最高位,即a[2]=1.
3.verilog 和matlab区别
verilog描述的时序电路并行,即移位寄存器反馈、移位、输出在同一个clk下,非阻塞赋值,所以三者之间没有先后顺序。
而matlab是按照语句先后顺序执行的。
所以分析,当寄存器载入初始值后,就先输出dout了,然后算反馈的值,注意此时不能立即将反馈值赋值给reg(1) ,(不能把当前reg(1)覆盖掉,当前reg(1)还没移位),而是暂存于tmp,因为要先完成移位后再赋值。
always @ ( posedge clk_in or negedge rst_n ) begin
if ( !rst_n ) begin
sr_rand <= 15'b0 ;
end
else if ( fd_in ) begin
sr_rand <= 15'b001001001001001;
end
else if ( start_rand ) begin
sr_rand[14] <= sr_rand[0] ^ sr_rand[1] ;
sr_rand[13:0] <= sr_rand[14:1] ;
end
else begin
sr_rand <= sr_rand ;
end
end
always @ ( posedge clk_in or negedge rst_n ) begin
if ( !rst_n ) begin
data_out <= 1'b0 ;
end
else if ( start_rand ) begin
data_out <= data_in_d ^ sr_rand[0] ^ sr_rand[1] ;
end
else begin
data_out <= 1'b0 ;
end
end
matlab:
function dout=scramble(din,N)
%g=1+x-14+x-15
n=mod(length(din),N);
d=[din, zeros(1,N-n)];
frmNum=length(d)/N;
for j=1:frmNum
reg_ini = [0 0 1 0 0 1 0 0 1 0 0 1 0 0 1];
reg = reg_ini;
for i = 1+(j-1)*N:N+(j-1)*N
dout(i)=xor(xor(d(i) , reg(14)) , reg(15));
tmp=xor(reg(14) , reg(15));
reg(2:15)=reg(1:14);
reg(1) = tmp;
end
end
end
verilog完整程序
外来信号都打一拍,使其同步
fd_in_d <= fd_in;
data_in_d <= data_in;
start_rand <= data_en;
装载数据sr_rand <= 15’b001001001001001;是类似于一个初始化的过程,所以其控制信号是fd_in,而不是fd_in_d.
module scrambler (
clk_in,
rst_n,
fd_in,
data_en,
data_in,
fd_out,
data_out_en,
data_out
);
input clk_in;
input rst_n;
input fd_in;
input data_en;
input data_in;
output reg fd_out;
output reg data_out_en;
output reg data_out;
reg [14:0] sr_rand;
reg fd_in_d;
reg data_in_d;
reg start_rand;
always @ ( posedge clk_in or negedge rst_n ) begin
if ( !rst_n ) begin
start_rand <= 1'b0 ;
data_in_d <= 2'b0 ;
fd_in_d <= 1'b0 ;
fd_out <= 1'b0;
data_out_en <= 1'b0;
end
else begin
start_rand <= data_en ;
data_in_d <= data_in ;
fd_in_d <= fd_in ;
fd_out <= fd_in_d;
data_out_en <= start_rand;
end
end
always @ ( posedge clk_in or negedge rst_n ) begin
if ( !rst_n ) begin
sr_rand <= 15'b0 ;
end
else if ( fd_in ) begin
sr_rand <= 15'b001001001001001;
end
else if ( start_rand ) begin
sr_rand[14] <= sr_rand[0] ^ sr_rand[1] ;
sr_rand[13:0] <= sr_rand[14:1] ;
end
else begin
sr_rand <= sr_rand ;
end
end
always @ ( posedge clk_in or negedge rst_n ) begin
if ( !rst_n ) begin
data_out <= 1'b0 ;
end
else if ( start_rand ) begin
data_out <= data_in_d ^ sr_rand[0] ^ sr_rand[1] ;
end
else begin
data_out <= 1'b0 ;
end
end
endmodule
tb
`timescale 1ns/1ps
module tb_scrambler();
reg clk_in;
reg rst_n;
reg fd_in;
reg data_en;
reg data_in;
wire fd_out;
wire data_out_en;
wire data_out;
initial begin
clk_in = 1'b0;
forever #20 clk_in = ~clk_in ;
end
initial begin
rst_n = 1'b0 ;
#50 rst_n = 1'b1 ;
end
initial begin
fd_in = 1'b0 ;
#70 fd_in = 1'b1;
#40 fd_in = 1'b0 ;
end
initial begin
data_en = 1'b0 ;
#70 data_en = 1'b1;
#100000 $stop;
end
initial begin
data_in = 1'b0 ;
forever #40 data_in = data_in;
end
scrambler scrambler (
.clk_in(clk_in),
.rst_n(rst_n),
.fd_in(fd_in),
.data_en(data_en),
.data_in(data_in),
.fd_out(fd_out),
.data_out_en(data_out_en),
.data_out(data_out)
);
endmodule