这里的移位寄存器不是简单的向左移位将串行输入转换为并行输出,而且要保留最后一个周期的输入数作为下一次输出的最高位,代码如下所示:
module shift_reg(
clk,rst,din,dout//,ordy
);
input clk;
input rst;
input [7:0] din;
output [31:0] dout;//4个周期
//output ordy;
reg [1:0] count;
//reg aaa;
//3分频时钟,占空比33%
always @ (posedge clk or posedge rst) begin
if (rst) begin
count <= 0;
// aaa <= 0;
end
else if (count == 2'b10) begin
count <= 0;
// aaa <= 1;
end
else begin
count <= count + 1;
// aaa <= 0;
end
end
reg [31:0] zuobiancunchu;//256*6
reg rstdelay;
//移位寄存器,0001,0012,0123,【1234】,2345,3456.【4567】,5678,6789,【789 10】,不断左移,带黑框的进入FFT模块
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
zuobiancunchu <= 0;
rstdelay <= 1;
end
else if (rstdelay)
begin
zuobiancunchu[7:0] <= din;//第一个周期
rstdelay <= 0;
end
else begin
zuobiancunchu <= {zuobiancunchu[23:0], din};//左移,后输入的数在低位
end
end
reg [31:0] zuobian;
reg qushudelay;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
zuobian <= 0;
qushudelay <= 1;
end
else if (count == 2'b01 && qushudelay == 1)
begin//qushudelay == 1时,寄存器为0123
qushudelay <= 0;
end
else if (count == 2'b01)
begin
zuobian <= zuobiancunchu;
end
end
assign dout = zuobian;
endmodule
RTL仿真如下:
虽然是每4个周期输出一次,但是实际更新的数只有3个周期;只是在第一次输出时要等待4个周期,此时按照规律有点麻烦,可以按上述代码所示提前1个周期输出,即假如本来是每3个周期输出一次,在count=2时的输出改变为提早一个周期输出,即在count=1输出,只是在第一次输出时需要将第一次count=1排除,所以要加标志位qushudelay;