[SystemVerilog] signal bitwidth

其他 2018-09-13 07:32:17 阅读次数: 0

常写a[MSB:LSB] 这里的MSB和LSB都要求是常数（或常数表达式）

而如果写a[BASE -: WIDTH]或a[BASE +: WIDTH]则允许BASE改变（但WIDTH仍需为常数）

Ex: data[ii +:1] 等价于data[ii+1:ii]

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转载自blog.csdn.net/lbt_dvshare/article/details/81460250

[SystemVerilog] signal bitwidth

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